Disk drives are a cost effective data storage system for use with a computer or other data processing devices. As shown in FIG. 1, a disk drive 10 comprises a magnetic recording medium, in the form of a disk or platter 12 having a hub 13 and a magnetic read/write transducer 14, commonly referred to as a read/write head. The read/write head 14 is attached to, or formed integrally with, a suspension arm 15 suspended over the disk 12 and affixed to a rotary actuator arm 16. A structural arm 18, fixed to a platform 20 of the disk drive 10, is pivotably connected to the actuator arm 16 at a pivot joint 22. A voice coil motor 24 drives the actuator arm 16 to position the head 14 over a selected position on the disk 12.
As the disk 12 is rotated by a spindle motor (not shown) at an operating speed, the moving air generated by the rotating disk, in conjunction with the physical features of the suspension arm 15, lifts the read/write head 14 away from the platter 12, allowing the head to glide or fly on a cushion of air slightly above a surface of the disk 12. The flying height of the read/write head over the disk surface is typically less than a micron.
An arm electronics module 30 may include circuits that switch the head function between read and write operations and write drivers for supplying write current to the head 14 during write operations. The write current alters magnetic domains within the disk 12 to store data thereon. The arm electronics module 30 may also include a preamplifier electrically connected to the head 14 by flexible conductive leads 32. During read operations the preamplifier amplifies the read signals produced by the head 14 to increase the read signal signal-to-noise ratio. In the write mode, the preamplifier scales up the relatively low voltage levels representing the data bits to be written to the disk to a voltage range of about +/−6 to +/−10V. The preamplifier also shapes the write signal to optimize the data writing process.
The configuration and components of the electronics module 30 may vary according to the disk drive design, as will be understood by persons familiar with such technology. Although the module 30 may be mounted anywhere in the disk drive 10, a location proximate the head 14 minimizes signal losses and induced noise in the head signals during a read operation. A preferred mounting location for the module 30 comprises a side surface of the structural arm 18 as shown in FIG. 1.
As shown in FIG. 2, the disk 12 comprises a substrate 50 and a thin film 52 disposed thereover. During write operations current through a write head 14A alters magnetic domains of ferromagnetic material in the thin film 52 for storing the data bits as magnetic transitions. During read operations a read head 14B senses the magnetic transitions to determine the data bits stored on the disk 12.
In other data storage systems the head 14 operates with different types of storage media (not shown in the Figures) comprising, for example, a rigid magnetic disk, a flexible magnetic disk, magnetic tape and a magneto-optical disk.
The disk drive read head 14B comprises either a magneto-resistive (MR) sensor or an inductive sensor. The former produces a higher magnitude output signal in response to the magnetic transitions, and thus the output signal exhibits a greater signal-to-noise ratio than an output signal produced by the inductive sensor. The MR sensor is thus preferred, especially when a higher areal data storage density in the disk drive 10 is desired.
A DC (direct current) voltage of about 0.04V to 0.2V is supplied by the preamplifier to the read head terminals 54A and 54B via the conductive leads 32 for biasing the read head 14B. Magnetic domains in the thin film 52 passing under the read head 14B alter a resistance of the magneto-resistive material, imposing an AC (alternating current) component on the DC bias voltage, wherein the AC component represents the read data bits. The AC component is detected in the preamplifier, but has a relatively small magnitude (e.g., several millivolts) with respect to the DC bias voltage.
Operation of the preamplifier read circuits is not required during those times when data is not being read from the disk 12. Since power consumption is not typically an operational limitation for a desktop computer, the read circuits in the desktop computer disk drive system are maintained in an on state when data is not being read from the disk 12. This feature minimizes a turn-on time for the read circuits (specifically the turn-on time for preamplifier current mirrors operative when reading data) and ensures that the preamplifier processes the magnetic transitions from the beginning of the data read interval.
The desktop preamplifier may be switched to a semi-active state (idle mode) if the computer does not access the disk drive 10 for an extended length of time, and may be shut down to a very low power level (sleep mode) when the computer switches to a sleep state. The disk drive system 10 permits a relatively long (i.e., several microseconds to milliseconds) power-up time for the preamplifier to transition from the sleep or idle mode to one of the fully active modes (e.g., the read or the write mode).
In contrast to a desktop computer system, battery power conservation is a crucial design objective for mobile and portable computing devices and data processing systems, for stored music players and for other battery-operated devices that include a mass data storage system operative with a preamplifier. To minimize preamplifier power consumption and thereby conserve battery power, the preamplifier read circuits are turned off when data is not being read from the hard disk drive. For example, the read circuits are turned off during data writing. But to avoid data losses during a read operation and to provide high-speed data access, it is desired that the preamplifier read circuits turn-on and reach a desired steady state condition in less than about 100 ns.
Returning to FIG. 2, the output signal from the read head 14B, representing data bits read from the disk drive 10 and having an amplitude in a range of several millivolts, is input to a signal processing stage 102 followed by an output or buffer stage 104. Typically, both the signal processing stage 102 and the output stage 104 are included within the preamplifier. The output stage 104 scales up the head signal voltage to a peak voltage value in a range of several hundred millivolts and supplies the scaled-up signal to channel circuits of a channel chip 106. The channel chip 106 detects the read data bits from the voltage pulses, while applying error detection and correction processes to the voltage pulses.
FIG. 3 illustrates a conventional prior art output stage 104 of FIG. 2. A PMOSFET M2 is gated on to supply a reference current Iref0 (25 microamps in one embodiment) that is directed to a collector C of a bipolar junction transistor (BJT) Q1 (operating as a current mirror master) and to a gate G of an n-channel metal oxide semiconductor field effect transistor NMOSFET) M0 to turn on the NMOSFET M0. A source S of the PMOSFET M2 and a drain D of the NMOSFET M0 are connected to a positive power supply voltage VP (in one embodiment about 3.3 V) and a source S of M2 is connected to a base B of the transistor Q1. When the NMOSFET M0 is on, the BJT Q1 is gated on and the current Iref0 flows through the BJT Q1 and a resistor R11 to ground. As is known, the base current of a BJT can change over a five to one range due to the BJT fabrication process variations and due to temperature variations during operation. A resistor R7 operates as a pull down resistor for the NMOSFET M0 to ensure M0 supplies sufficient bias current for proper operation of the current mirror transistors Q1, Q2, Q3, Q4 and Q5 over all expected process, temperature and operating conditions. In those applications where battery power conservation is advisable, the current Iref0 is terminated when data is not being read from the disk 12, i.e., when data is being written to the disk 12 and during idle periods when data is neither being written nor read.
The BJTS Q2, Q3, Q4 and Q5 are also gated on by the on-state of the NMOSFET M0. Assuming that the BJTS Q1, Q2, Q3, Q4 and Q5 are matched, have substantially identical base-emitter voltages and operate with properly-scaled emitter resistors R11, R10, R13, R14 and R15, then the BJTS Q1, Q2, Q3, Q4 and Q5 operate as scaled current mirrors. By properly scaled emitter resistors is meant that each resistor R11, R10, R13, R14 and R15 is scaled based on the BJT with which the resistor is associated, i.e., R10=R11/k1, R13=R11/k2, R14=R11/k3 and R15=R11/k4, where k1-k4 represent an emitter area ratio for each of the BJT's Q2-Q5 relative to the emitter area of Q1, that is, Q2=Q1*k1, Q3=Q11*k2, Q4=Q1*k3 and Q5=Q1*k4). The BJTS Q2, Q3, Q4 and Q5 function as constant current sources for their associated BJTS Q7, Q6, Q12 and Q9. The current Iref0 through the BJT Q1 is mirrored and scaled (according to the associated scaling value k) through the BJTS Q2, Q3, Q4 and Q5.
A collector C of a BJT Q7 is connected to the power supply VP through a resistor R17, and a base B of Q7 is driven by a bias voltage (not shown) and voltage pulses from the signal processing stage 102. When an amplifier comprising BJTS Q6 and BJT Q7 is active, the BJT Q7 is driven to an on state or on condition and the current Iref through the BJT Q1 is mirrored as a current I2 through resistors R10 and R17 and the BJTS Q7 and Q2. Since the BJTS Q1 and Q2 form a current mirror, then I2=k1*Iref, where k1 is the ratio of the emitter area of BJT Q2 to the emitter area of BJT Q1. Typically such area ratioed BJTS are formed from a plurality of unit transistors, that is, the BJT Q2 comprises k1 times the number of unit transistors comprising the BJT Q1.
The negative feedback action of the emitter resistors R10 and R11 increases the impedance seen looking into the collector of the BJT Q1 and the BJT Q2 enough such that the ratio of I2 to Iref is a very weak function of Q2's collector-emitter voltage, as long as Q2's collector-emitter voltage is greater than approximately 0.5V. Thus as can be appreciated by those skilled in the art, the variation of I2 with the collector-emitter voltage of BJT Q2 is neglected herein.
A state of the current mirror BJT Q3 is controlled by the NMOSFET M0. The BJT Q6 is biased by the signal processing stage 102, which supplies both the signal and DC bias to the base B of the BJT Q6. When the BJTS Q3 and Q6 are both gated on, a current I3 flows through resistors R19 and R13 and the BJTS Q3 and Q6, where I3=k2*Iref, since the BJTS Q1 and Q3 are current mirrors and Q3=Q1*k2.
The BJTS Q6 and Q7 form a differential amplifier with a degeneration resistor R20 connected between the emitter of the BJT Q6 and the emitter of the BJT Q7 to linearize the amplification and stabilize the gain. The signal from signal processing stage 102 biases the amplifier inputs (the base of each one of the BJTS Q6 and Q7) and presents the processed data signal that is amplified (i.e., scaled-up) and buffered by the output stage 104 before driving an interconnect to the channel chip 106, i.e., terminals RDP and RDN.
The BJTS Q9 and Q12 buffer collector loads R17 and R19 to drive the interconnect to the channel chip 106 from a low impedance thereby maintaining a wide bandwidth, typically up to about 700 MHz.
In FIG. 3 the NMOSFET M0 supplies the base drive current for each of the current mirror BJTS Q1, Q2, Q3, Q4 and Q5. In one embodiment each BJT base current is about 16 microamps, for a total of about 80 microamps. The current Iref is substantially equivalent to the collector current of the BJT Q1, since substantially no current flows to the gate G of the NMOSFET M0.
A circuit loop comprising the base/collector path of the BJT Q1 and the gate/source path of the NMOSFET M0 forms a feedback loop that, like all feedback loops, tends to oscillate. The oscillations are limited or controlled by a capacitor C0 connected between the collector of the BJT Q1 and ground. The loop bandwidth is controlled by the current through the NMOSFET M0, as determined by the resistor R7 and is increased by the base current supplied to the BJTS Q1, Q2, Q3, Q4, and Q5.
Although the capacitor C0 advantageously prevents feedback loop oscillation, it also disadvantageously extends the turn-on time of the current mirror BJTS Q1, Q2, Q3, Q4 and Q5 as the current mirrors do not turn on until the capacitor C0 has charged. The output signal does not appear at the terminals RDP and RDN until the current mirrors have turned on. Thus the output signal is delayed by the charging time of the capacitor C0. In certain embodiments of the output stage 104 the output signal delay exceeds the objective of about 100 nanoseconds.